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Automatic RF MESFET Amplifier
Drain-Current Controllers
Set the LDAC1 bit, D5, to 1 to load the new value of
V DAC1 , upon completion of a V DAC1(CODE) calculation,
into both the channel 1 DAC input and output registers.
Set to 0 to load the new value of V DAC1 , upon comple-
tion of a V DAC1(CODE) calculation, to only the channel 1
DAC input register. Set the T1COMP1/0 bits, D4 and
D3, to control the channel 1 temperature LUT. See
Table 11a. Set the KSRC1-2/1/0 bits, D2, D1, and D0 to
control the channel 1 K parameter LUT. See Table 11b
and the SRAM LUTs section.
Set the channel 1/channel 2 DAC code by writing to the
respective channel’s DAC input registers, DAC input
and output registers, or V SET registers. Write to the
DAC input registers (Table 16) and use a subsequent
write to the software load DAC register (Table 21) to
control the timing of the update. Write to the DAC input
and output registers (Table 17) to set the DAC output
voltage code directly, independent of the software load
DAC register bits. Write to the V SET registers (Table 14)
to include LUT data in the DAC code. Writing to the
V SET registers triggers a V DAC(CODE) calculation by the
following equation:
V DAC ( CODE ) = V SET ( CODE ) ( 1 + LUT K [ K ] x LUT TEMP [ TEMP ])
where
V DAC(CODE) = The modified channel1/channel 2 12-bit
DAC code.
V SET(CODE) = The 12-bit DAC code written to the chan-
nel 1/channel 2 V SET registers.
LUT K [K] = The interpolated, fractional 12-bit KLUT
value. The KLUT data is derived from a variety of
sources, including the V SET register value, the K para-
meter register value, or various ADC channels. See the
SRAM LUTs section.
LUT TEMP [TEMP] = The interpolated, fractional 12-bit
two’s-complement temperature LUT value. The tempera-
ture LUT data is derived from either internal or external
temperature values.See the SRAM LUTs section.
When the KSRC_-2/KSRC_-1/KSRC_-0 bits are set to
000 and T_COMP1/T_COMP0 bits are set to 00 or 01,
the V DAC(CODE) equation simplifies to:
V DAC ( CODE ) = V SET ( CODE )
Note: This is a special case and will not trigger a
V GATE calculation unless a sample already exists. This
functionality should be accessed by the THRUDAC reg-
isters.
For temperature samples or sampled KLUT sources to
automatically trigger V DAC(CODE) calculations, the ADC
must be configured to provide these samples.
Therefore, the ADC conversion register (Table 19) must
have the relevant channel bits set and the ADC must be
in a suitable clocking mode, regardless of the
ADCMON bit setting.
CHANNEL 1/CHANNEL 2 DAC
INPUT REGISTERS:
LDAC
CHANNEL 1/CHANNEL 2 DAC
INPUT AND OUTPUT REGISTERS:
(IPDAC1/IPDAC2
THRUDAC1/THRUDAC2)
REGISTER
CHANNEL 1/ CHANNEL 2 DAC
OUTPUT VOLTAGE
(THRUDAC1/
THRUDAC2)
V DAC CALCULATION
LDAC_ BITS
SET TO 1 IN
SCFG REGISTER
Figure 20. DAC Register Format
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37
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